The invention relates to an apparatus and method for testing bare dies.
A classical problem in the assembly of any hybrid circuit, comprising a number of unpackaged integrated circuit (IC) devices to be assembled on an appropriate circuit interconnection substrate, is connected with the fact that the probability that each chip in the assembly is actually functional is less than unity. The yield of the assembled hybrid is then the product of all the individual chip yield probabilities and the assembly yield, or, expressed mathematically: EQU Y=(F.multidot.(B).sup.m).sup.n
where Y =final circuit yield
Y=final circuit yield PA1 F=probability that an IC is functional PA1 B=probability of forming individual IC to substrate connection PA1 m=number of connections per chip PA1 n=number of ICs in the circuit assembly
In order to obtain high circuit yield, it is essential that every IC is functional prior to committing it to the assembly and that a very high yield assembly process is employed. The flip chip solder bonding technique, for example, in which an array of solder bumps are provided over the contact pads on the naked IC and the IC attached to the substrate in an inverted attitude, has been shown to provide an appropriately high yield assembly method. In uncooled IR detector arrays, for example, 100% bond yield has been obtained in devices with 10,000 solder bond connections, implying an individual bond yield of 99.99% or better.
Unfortunately-with the use of naked, unpackaged ICs, such as are employed in many forms of hybrid circuit construction, the individual IC probability of functionality is not as high as this. More typical figures are between 90% and 99%. This is largely due to the difficulty of testing bare, unpackaged ICs thoroughly, particularly at the final operating frequency, and also, in part, to the statistical nature of testing high complexity devices where the test patterns can only sample a portion of the device's functional requirements. This then means that, as the number of ICs in the assembly increase, the circuit yield will decrease and rapidly approach the point where it becomes unacceptably low.
There is therefore a clear requirement to devise an apparatus and method that ensure high individual IC functional confidence or device "goodness" for the assembly of bare die hybrid circuits.
Silicon integrated circuit devices (SICs) are processed in wafer form and initial device testing is conducted on the completed wafer prior to dicing using a probe card or, more recently, a membrane probe card, to make electrical contacts to the contact pads of the ICs under test. A conventional probe card comprises a radial array of metallic probes supported in a circular aperture on a printed circuit board. The probes are provided with fine probe tips, commonly fabricated using fine tungsten wire which has been formed to a spherical tip shape at the point of contact, with a typical tip diameter of 50 .mu.m. These tungsten probes are typically 0.5 mm in length and 0.15 mm diameter. Contact forces of 6 to 8 grams per probe are employed to ensure that low contact resistance to the aluminium alloy metallisation pads on the IC is obtained. A probe set is expected to provide some 0.5 million touch downs before replacement. The probes are independently mounted and adjusted to ensure consistent contact. Tungsten is selected as the probe material since it provides high hardness for a low probe wear rate and low electrical resistivity for low probe resistance.
Device tests on wafer include basic parametric tests, low frequency functional testing and, in some cases, speed binning tests using specially designed test structures, or boundary scan testing. The relatively high resistance and particularly the inductance of the conventional probe card arrangement, however, precludes thorough device testing at full operating frequency. A further constraint on wafer level testing is associated with the finite test time required to conduct a comprehensive functional test. The mechanical difficulties associated with constricting conventional probe cards for very high pin count ICs is one reason that alternative probe card approaches are now being examined.
Once the ICs that have passed the wafer level probe testing have been packaged, then comprehensive functional testing can proceed. The package provides mechanical protection for the IC, to allow straightforward device handling in the test system feeder, and also a practical means of making contact to the device under test through the package leads.